1. Field of the Invention
The present invention is directed to digital loops and, more particularly, to reduction of effects of digital loop dead zones.
2. Related Art
Digital loops, such as phase locked loops (“PLLs”), operate at discrete time intervals, marked by clock edges. When an asynchronous signal, such as a feedback signal and/or a digital reference signal, is synchronized with a digital loop system clock, information is essentially truncated to the nearest system clock. As a result, conventional digital loops can only measure the phase of the signal to the nearest clock edge. Conventional digital loops cannot distinguish phase changes in regions centered between clock edges. The central region is thus referred to herein as a dead zone. The dead zones are essentially equal to the clock period.
Digital loop dead zones cause non-ideal loop behavior and result in a loss of phase information. For example, when a digital loop is locked, the loop tends to wander about the dead zone. Additionally, when the reference signal changes, the loop takes longer to respond to the change.
What are needed, therefore, are methods and systems for reducing effects of digital loop dead zones.